This invention relates generally to the field of delay locked loops. More particularly, certain embodiments consistent with this invention relate to compensation of individual delay variations in delay line elements used in a digital to phase converter.
A more or less conventional delay locked loop circuit 20 is depicted in FIG. 1.
In this delay locked loop circuit 20, a delay line 24 is made up of a plurality of cascaded controlled delay elements 32, 34, 36 through 38, each having an input and an output In delay line 24, N such delay elements are provided each having a delay D. Such a delay line can be implemented using, for example, a series of inverter buffers, each with a voltage controlled delay for adjustment of the value of D. Thus, delay line 24 has an overall delay of Nxc3x97D. The overall delay of delay line 24 is tuned by a voltage (or other suitable control signal) applied to a control input 44. A suitable signal applied to input 44 simultaneously adjusts the delays of each of the N delay elements (which are preferably closely matched) to produce an overall adjustment in the delay Nxc3x97D. A tapped output is available at each of the delay elements 32, 34, 36 through 38 having a total amount of delay dependent upon the number of delay elements encountered from the input of the delay line 24.
In delay locked loop 20, a clock signal FREF is applied to an input 48 and, after encountering Nxc3x97D delay, exits at output 52. The output at 52 and the input at 48 are each applied to a phase detector 56 that produces an output that represents the difference in phase between the two inputs. This output is filtered by a low pass filter 60. The output of the low pass filter 60 drives the control input 44 to effect a tuning of the delay line 24 so that the delay line 24 is adjusted to produce an output at output 52 that is a total of a predetermined delay from the input signal applied at input 48. One choice for the delay would be one input clock cycle or 1/FREF. In order to produce accurately synthesized signals at the output 66 of multiplexer 70, the delays associated with each delay element 32, 34, 36, . . . , 38 should be equal.
A delay locked loop (DLL) synthesizer as shown in FIG. 1 can potentially be used as a frequency synthesizer in many electronic devices such as wireless telephones (e.g., cellular telephones), two-way radio transceivers, radio transmitters and radio receivers. Such synthesizers are sometimes referred to as digital to phase converters (DPC). However, to effectively use a DLL in such applications, frequency output should be accurate and relatively free of errors caused by manufacturing variations in the delay of the delay elements.